1. Field of the Invention
The present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to various methods of making a semiconductor device by implanting hydrogen or hydrogen-containing clusters to improve the interface between a gate insulation layer and the substrate.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NMOS and PMOS transistors) represent one important type of circuit elements that substantially determine performance of the integrated circuits. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., NMOS transistors and/or PMOS transistors are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed between the highly doped regions source/drain regions.
In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode that is formed adjacent to the channel region and separated therefrom by a thin gate insulation layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends upon, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as the channel length of the transistor. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors.
For many early device technology generations, the gate electrode structures of most transistor elements has comprised a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate electrode stacks comprising alternative materials in an effort to avoid the short-channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in PMOS transistors, the channel region may be comprised of a layer of silicon germanium that is formed in the substrate. As another example, in some aggressively scaled transistor elements, which may have channel lengths of on the order of approximately 14-32 nm, gate electrode stacks comprising a so-called high-k dielectric/metal gate (HK/MG) configuration have been shown to provide significantly enhanced operational characteristics over the heretofore more commonly used silicon dioxide/polysilicon (SiO/poly) configurations.
Depending on the specific overall device requirements, several different high-k materials—i.e., materials having a dielectric constant, or k-value, of approximately 10 or greater—have been used with varying degrees of success for the gate insulation layer in a HK/MG gate electrode structure. For example, in some transistor element designs, a high-k gate insulation layer may include tantalum oxide (Ta2O5), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), hafnium silicates (HfSiOx), and the like. Furthermore, one or more non-polysilicon metal gate electrode materials—i.e., a metal gate stack—may be used in HK/MG configurations so as to control the work function of the transistor. These metal gate electrode materials may include, for example, one or more layers of titanium (Ti), titanium nitride (TiN), titanium-aluminum (TiAl), aluminum (Al), aluminum nitride (AlN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum silicide (TaSi), and the like.
Irrespective of the material of the gate insulation layer, e.g., silicon dioxide or a high-k material, and irrespective of the materials of the underlying substrate, e.g., silicon or silicon germanium, there are always imperfection at the interface between the gate insulation layer and the substrate. Such imperfections may be caused by a variety of factors, such as, for example, mismatched crystal lattice structures, different material phases, etc. These imperfections at the interface result in open bonds, so-called dangling bonds, that act to trap charge carriers like electrons (NMOS devices) or holes (PMOS devices) as current is flowing through the device. This trapping reduces the electrical performance capability of the device as some of the charge carriers are bonded to the dangling bonds.
One effective technique that has been employed in the past to overcome the problem of dangling bonds is to anneal the device in a high pressure deuterium (D2) ambient. Such a treatment tends to eliminate virtually all of the dangling bonds and typically results in significant improvement in the performance of the final device. However, there are several problems or issues that must be confronted when using such a deuterium treatment technique. For example, the deuterium treatment technique typically is a high-pressure process (e.g. a pressure of about 8 bars) and it involves the use of expensive equipment and materials. Overall, such a process is just generally difficult to deal with given the high pressures involved and, everything considered, it is a relatively expensive process.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.